Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to threshold voltage adjustment of long-channel MOS transistors.
State of the Art
Metal-Oxide-Semiconductor (MOS) is the primary technology for large-scale integrated semiconductor circuits. In Complementary MOS (CMOS) architectures, these semiconductor circuits combine two types of MOS devices, namely p-channel MOS (PMOS) devices and n-channel MOS (NMOS) devices, on the same integrated circuit. An MOS transistor is a four-terminal device which controls the current that flows between two of the terminals by activating and deactivating the voltage that is applied to the third or fourth terminal. FIG. 1 shows a cross-sectional diagram of a conventional n-channel MOS transistor 10. As shown in FIG. 1, transistor 10 includes spaced-apart n+ source and drain regions 12 and 14, which are formed in a p-type substrate 16 and a channel region 18, which is defined between source and drain regions 12 and 14. Source and drain regions 12 and 14, in turn, represent the first two terminals of the device while substrate 16 represents the third terminal.
Transistor 10 also includes a layer, illustrated as gate oxide 20, which is formed over channel region 18, and a gate 22 which is formed over gate oxide 20. Gate 22 represents the fourth terminal of the device. During operation of the transistor 10, electrons flow from source region 12 to drain region 14 when an electric field is established between source and drain regions 12 and 14. Furthermore, the drain-to-substrate junction is reverse biased when a gate voltage equal to or greater than the threshold voltage of transistor 10 is applied to gate 22. These conditions can be met, for example, when ground is applied to substrate 16 and source region 12, and one volt, for example, is applied to drain region 14.
A gate voltage applied to gate 22 attracts electrons to the surface adjacent to gate oxide 20 of substrate 16 in channel region 18. When a minimum number of electrons have been attracted to the surface of substrate 16 in channel region 18, the electrons form a channel that allows the electrons in source region 12 to flow to drain region 14 under the influence of the electric field. The threshold voltage is defined as the minimum gate voltage that must be applied to gate 22 to attract the minimum number of electrons to the surface of substrate 16 to form an electrically conductive inversion region in the channel region 18.
The threshold voltage of transistor 10 may be altered or adjusted by implanting the surface of substrate 16 in channel region 18 with, for example, a p-type dopant which, in turn, decreases the number of electrons that can be accumulated at the surface in the channel region 18. Since fewer electrons are available, a higher gate voltage is needed to attract the minimum number of electrons that are required to form an inversion layer in the channel region 18. A threshold voltage adjustment implant is commonly referred to as an “enhancement” implant.
MOS transistors are formed using photolithographic processes according to design rules corresponding to a particular process. The design rules specify, among other things, the minimum length of the channel region. To gain performance advantages and as processing technology advancements have been achieved, the channel length between the source and drain has generally shortened. Furthermore, to minimize the silicon area consumed by an MOS circuit, a typical integrated circuit design is largely implemented with transistors that have the minimum channel length. Since the circuit is largely implemented with transistors that have the minimum channel length, the fabrication process, for example, the enhancement implant, is commonly optimized to adjust the threshold voltages of the transistors that have the minimum channel length. While performance improvement is generally a paramount objective for MOS circuit design, it is common for circuits, in addition to utilizing transistors having minimum channel length, to also require transistors that have channel lengths that are longer than the minimum. For those transistors with a longer channel length, a lower threshold voltage is realized when the threshold voltage is optimized for a shorter channel transistor through the use of a single enhancement implant.
FIG. 2 is a graph that generally plots the threshold voltages as a function of channel length. As shown in FIG. 2, when the threshold voltage is optimized for an arbitrary fabricable channel length x, the threshold voltage of a transistor decreases as the channel length of the transistor increases. Furthermore, the reduced threshold voltages of the longer channel devices lead to increased leakage currents which, in turn, are particularly undesirable in circuits that are utilized in battery-operated devices.
One prior solution to this problem is to utilize multiple threshold voltage adjusting enhancement implants. In a first step, dopants are implanted into the surface of the substrate to adjust the threshold voltages of the short-channel transistors while the long-channel transistors are protected from the implant. In a second step, dopants are implanted into the surface of the substrate to adjust the threshold voltages of the long or longer channel transistors while the short-channel transistors are protected from the implant. By utilizing, for example, two implant steps, the dopant concentration for the short and long-channel lengths can be separately optimized.
One shortcoming to the multiple-threshold adjusting implant approach, however, is that utilizing separate implant steps requires separate masks which, in turn, increases the cost of fabricating the circuit. Thus, there is a need for adjusting the threshold voltage of long-channel MOS transistors to a higher threshold voltage when the long-channel transistor is fabricated with a single threshold-voltage implant step that is optimized to set the threshold voltage of a short-channel transistor.